Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
User designs often require cascading of interconnected configurable resources (e.g., outputs of LUTs feeding a next level of LUTs) when synthesized. This cascading of configurable resources leads to an increased propagation delay, which in turn results in an increased clock period and reduced clock frequency for the PLD. Moreover, such user designs may also waste configurable resources and interconnections, especially if some of the configured resources are only partially utilized.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.